The present invention relates to a semiconductor device employing dielectric isolation for insulation between elements, and in particular, to a semiconductor device for optimally controlling a power device for driving a high power motor.
A dielectric isolation semiconductor device (semiconductor device employing dielectric isolation for insulation between elements) is sometimes employed as a semiconductor device for controlling a power device. The dielectric isolation semiconductor device is a semiconductor device in which a high breakdown voltage element, a high current output circuit and a low breakdown voltage logic circuit are integrated together, for example, and each element is surrounded by dielectric material (e.g. silicon dioxide film) and thereby insulated from the substrate and other elements against high voltage. For example, a dielectric isolation semiconductor device for driving a motor includes various circuits such as a gate driving circuit of the high-voltage circuit section, a high breakdown voltage MOS transistor for supplying a control signal to the high voltage side gate driving circuit, and a control logic circuit.
FIG. 12 is a cross-sectional view showing a high breakdown voltage n-type MOS transistor which is formed in a dielectric isolation semiconductor device having conventional structure. In FIG. 12, the reference numeral “101” denotes a source electrode, “102” denotes a gate electrode, and “103” denotes a drain electrode. The source electrode 101 is electrically connected to an n+ heavily doped source region 110 and a p+ heavily doped source region 120 by ohmic contact. The drain electrode 103 is electrically connected to an n+ heavily doped drain region 130 by ohmic contact.
A p-type channel region 140 is a p-type doped region, in which an n-channel inversion layer is formed right under the gate electrode 102. These n-type/p-type regions are formed on a silicon substrate that is called a “SOI (Silicon On Insulator) substrate”.
The SOI substrate is a substrate made up of a silicon support substrate 105, a silicon dioxide layer 106 and a silicon active layer 108. The silicon dioxide layer 106, sandwiched between the silicon support substrate 105 and the silicon active layer 108, will hereinafter be referred to as an “embedded oxide layer”.
In the silicon active layer 108, a dielectric isolation region 107 for electrically isolating the element from surrounding regions is formed as a substantially vertical region reaching from the primary surface of the silicon active layer 108 to the embedded oxide layer 106. The dielectric isolation region 107 includes silicon dioxide films 171 (formed as side walls on both sides) and a polysilicon layer 172 embedded in the gap between the silicon dioxide films 171. In prescribed areas on the primary surface of the silicon active layer 108, thick silicon dioxide layers 150 (hereinafter referred to as “field oxide layers”) are formed, by which the p-type/n-type doped regions on the primary surface of the silicon active layer 108 are separated from each other. Over the field oxide layers 150, a CVD layer 109 (made of silicon dioxide) is formed.
In the above element having the conventional structure, a p-type impurity diffusion region 131 is formed under the field oxide layer 150 between the source electrode 101 and the drain electrode 103 so that the OFF state (no current flowing between the source and the drain) can be maintained even when high voltage is applied to the source electrode 101 and the drain electrode 103. The p-type impurity diffusion region 131 is connected to the p-type channel region 140.
Incidentally, the p-type impurity diffusion region 131 in the cross-sectional view of FIG. 12, which looks as if two separate regions 131 are placed on both sides of the n+ heavily doped drain region 130, is actually one region formed continuously. Thus, the above element having the conventional structure is characterized by a connection configuration that restricts one side by the electric potential of the p-channel region.